Laser thermal processing (LTP) is used to process workpieces such as semiconductor wafers in the manufacturing of semiconductor devices. Such processing allows for the fabrication of transistors with very low sheet resistance and ultra-shallow junctions, which results in a semiconductor device (e.g., an integrated circuit or "IC") having higher performance (e.g., faster speed).
One method of LTP applied to semiconductor manufacturing involves using a short-pulsed laser to thermally anneal the source and drain of the transistor and to activate the implanted dopants therein. Under the appropriate conditions, it is possible to produce source and drain junctions with activated dopant levels that are above the solid solubility limit. This produces transistors with greater speeds and higher drive currents. This technique is disclosed in U.S. Pat. No. 5,908,307 entitled "Fabrication Method for Reduced Dimension FET Devices," incorporated by reference herein.
It is expected that ICs will benefit from the performance improvement demonstrated with performing LTP on single transistors. Unfortunately, scaling LTP from single transistor fabrication to full integrated circuit fabrication is difficult. The LTP process has a very narrow process window (i.e., the range in laser energy that activates the transistor without causing damage is narrow) and requires considerable uniformity, stability and reproducibility in the absolute energy delivered to (and absorbed by) each transistor.
Modern ICs contain a variety of device geometries and materials, and thus different thermal masses. To achieve uniform performance in each transistor, it is necessary that all transistors be heated (annealed) to essentially the same temperature. This places constraints on the permissible range of laser energy delivered to each transistor in the circuit. As a result, two problems arise. The first is that it is difficult to achieve sufficiently uniform exposures (both spatially and temporally) to accomplish uniform heating. The second is that different device geometries require different amounts of incident laser energy because their different thermal masses will affect the local temperature in the doped regions (junctions).
Of these two problems, the more daunting is the effect of local transistor density. Most modern integrated circuits have a variety of transistor densities across the circuit. This variation has two effects on the LTP process. The first is that the local reflectivity varies spatially, thereby changing the amount of heat locally absorbed even with uniform illumination. The second is that the local thermal mass varies spatially. A larger thermal mass requires greater absorbed laser energy to reach the required annealing temperature. As a result, a change in the local thermal mass requires a change in the amount of laser energy absorbed that is required to produce proper annealing. Even with perfectly uniform illumination, there can be significant temperature variations between different transistors on a single IC, or between ICs. This leads to undesirable variations in transistor performance across a single IC and across a product line.
In principle, it may be possible to compensate for the location of higher transistor density across the device by providing a tailored exposure having increased laser fluence in the higher density regions. However, this would require knowing the precise circuit layout across the device for each device to be processed, and would also require precise tailoring of the spatial irradiance distribution of the exposure to match the circuit layer. This endeavor, if it could be accomplished at all, would involve complex apparatus and significant expense.